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Hi there! I am an MS/PhD student at Cornell University. I am advised by Prof. Zhiru Zhang. I am interested in Electronic Design Automation, Domain-Specific Language for hardware design, and hardware accelerators.
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Department: 
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Office: 471B Rhodes Hall
News
🎊 Our journal paper RapidLayout won the Best Paper Award for ACM TRETS in 2023. [Award Plaque] (07/13/23) Donated my hair to Locks of Love to support children suffering from hair loss. [Certificate of Appreciation] (07/04/23) Our journal paper has been selected as the Featured Paper of IEEE Trans. on Computers. (05/11/23) Our patent CN109658402B has been granted. [Certificate] [Google Patents] (04/18/23) Selected as DAC Young Fellow [Certificate] (04/08/23) |
Education
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M.S./Ph.D. in Electrical and Computer Engineering |
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B.Eng. in Telecommunication Engineering |
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Work Experience
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Compiler Intern |
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Exempt Tech Employee |
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Research Assistant |
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MITACS
Research Intern |
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Research & Publication
My research interests include EDA (Electronic Design Automation) for FPGA, DSL (Domain-Specific Language), and efficient machine learning. |
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Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gaberiel Rodríguez, Zhiru Zhang FPGA 2024, to appearWe target the problem of efficiently checking the semantics equivalence between two programs written in C/C++ as a means to ensuring the correctness of the description provided to the HLS toolchain, by proving an optimized code version fully preserves the semantics of the unoptimized one. |
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Courtney Golden, Dan Ilan, Caroline Huang, Niansong Zhang, Zhiru Zhang, Christopher Batten IEEE Computer Architecture Letters | paperWe implement a virtual vector instruction set on a commercial Compute-in-SRAM device, and perform detailed instruction microbenchmarking to identify performance benefits and overheads. |
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Shulin Zeng, Guohao Dai, Niansong Zhang, Xinhao Yang, Haoyu Zhang, Zhenhua Zhu, Huazhong Yang, Yu Wang IEEE Transactions on Computers | paper
This paper proposes a Design Space Exploration framework to jointly optimize heterogeneous multi-core architecture, layer scheduling, and compiler mapping for serving DNN workloads on cloud FPGAs. |
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Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang Invited Paper, DAC 2022, paperWe show the advantages of the decoupled programming model and further discuss some of our recent efforts to enable a robust and viable verification solution in the future. |
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Tianchen Zhao, Niansong Zhang, Xuefei Ning, He Wang, Li Yi, Yu Wang CVPR 2022, paper | website | slides | poster | videoWe propose a flexible 3D Transformer on sparse voxels to address transformer's generalization issue. CodedVTR (Codebook-based Voxel TRansformer) decomposes attention space into linear combinations of learnable prototypes to regularize attention learning. We also propose geometry-aware self-attention to guide training with geometric pattern and voxel density. |
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Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang FPGA 2022, paper | codeWe propose an FPGA accelerator programming model that decouples the algorithm specification from optimizations related to orchestrating the placement of data across a customized memory hierarchy. |
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Niansong Zhang, Xiang Chen, Nachiket Kapre
Volume 15, Issue 4, Article No.: 38, pp 1–23 We extend the previous work on RapidLayout with cross-SLR routing, placement transfer learning, and placement bootstrapping from a much smaller device to improve runtime and design quality. |
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Xuefei Ning, Changcheng Tang, Wenshuo Li, Songyi Yang, Tianchen Zhao, Niansong Zhang, Tianyi Lu, Shuang Liang, Huazhong Yang, Yu Wang Arxiv Preprint, paper | codeWe build an open-source Python framework implementing various NAS algorithms in a modularized and extensible manner. |
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Niansong Zhang, Xiang Chen, Nachiket Kapre FPL 2020, paper | code
We build a fast and high-performance evolutionary placer for FPGA-optimized hard block designs that targets high clock frequency such as 650+MHz. |
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Hongzheng Chen*, Niansong Zhang*, Shaojie Xiang, Zhiru Zhang MLIR Open Design Meeting (08/11/2022) | video | slides | website
CRISP Liaison Meeting (09/28/2022) | news | slides | website 
We decouple hardware customizations from the algorithm specifications at the IR level to: (1) provide a general platform for high-level DSLs, (2) boost performance and productivity, and (3) make customization verification scalable. |
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Shulin Zeng, Guohao Dai, Niansong Zhang, Yu Wang MICRO 2021 ASCMD Workshop, paper | videoWe propose a multi-node and multi-core accelerator architecture and a decoupled compiler for cloud-backed INFerence-as-a-Service (INFaaS). |
Workshops & Talks
![[Award Plaque]](https://res.cloudinary.com/dxzx2bxch/image/upload/v1690679896/IMG_8702_zyhgkc.jpg){kind=link}
![[Certificate]](https://res.cloudinary.com/dxzx2bxch/image/upload/v1690679896/IMG_8739_uxxdro.jpg){kind=link}
Professional Services
Student Volunteer: FCCM’22 Reviewer: ICCAD 2022, 2023, TRETS, TCAS II |
Teaching
[ECE 5775] High-Level Digital Design Automation Part-time TA, Fall 2022 |
Awards and Honors
Best Paper Award for ACM TRETS in 2023 DAC Young Fellow 2021 & 2023 FPL 2020 Best Paper Nomination (Michal Servit Award) Outstanding Bachelor Thesis Award | Sun Yat-sen University Mitacs Globalink Research Internship Award | Mitacs, Canada First-class Merit Scholarship x2 | Sun Yat-sen University Lin and Liu Foundation Scholarship | SEIT, Sun Yat-sen University |
Patents
Niansong Zhang, Songyi Yang, Shun Fu, Xiang Chen, "Industry Profile Geometric Dimension Automatic Measuring Method Based on Computer Vision Imaging." Chinese Patent CN201811539019.8A, filed December 17, 2018, and issued April 19, 2019. Niansong Zhang (at Novauto Technology), "A Pruning Method and Device of Multi-task Neural Network Models", Chinese Patent 202010805327.1, filed August 12, 2020. |