Hi there! I am an MS/PhD student at Cornell University, advised by Prof. Zhiru Zhang. I am interested in Electronic Design Automation, Domain-Specific Languages for hardware design and programming, and hardware accelerators.
M.S./Ph.D. in Electrical and Computer Engineering
Advisor: Prof. Zhiru Zhang
B.Eng. in Telecommunication Engineering
Advisor: Prof. Xiang Chen · Outstanding thesis
PhD Research Intern · Design Automation Research
Mentor: Anthony Agnesina, Chenhui Deng, Mark Ren
Compiler Intern · ACDC, CTO
Manager: Stephen Neuendorffer
Exempt Tech Employee · SAVE Group
Manager: Jin Yang, Sunny Zhang
I build compilers, programming models, and design automation tools that make it easier to design and program specialized hardware.
We introduce MLIR-AIR, an open-source compiler stack built on MLIR that bridges the semantic gap between high-level workloads and fine-grained spatial architectures such as AMD's NPUs, achieving up to 78.7% compute efficiency on matrix multiplication.
MICRO 2025 · paper
This paper characterizes a commercial compute-in-SRAM device using realistic workloads, proposes key data management optimizations, and demonstrates that it can match GPU-level performance on retrieval-augmented generation tasks while achieving over 46x energy savings.
MLCAD 2025 · paper
ASPEN uses LLM-guided e-graph rewriting with real PPA feedback for RTL optimization. With 16.51% area and 6.65% delay improvements over prior methods, ASPEN shows you can have both smart and sound—and it's fully automated.
Best Paper Award
We present Cypress, a GPU-accelerated, VLSI-inspired PCB placer that boosts routability by up to 5.9x, cuts track length by 19.7x, and runs up to 492x faster on new realistic benchmarks.
Best Paper Nominee
We propose ARIES, a unified MLIR-based compilation flow that abstracts task, tile, and instruction-level parallelism across AMD AI Engine arrays (and optional FPGA fabric), boosting Versal VCK190 GEMM throughput by up to 1.6x over prior work.
Allo, a new composable programming model, decouples hardware customizations from algorithms and outperforms existing languages in performance and productivity for specialized hardware accelerator design.
Best Paper Award
We target the problem of efficiently checking the semantics equivalence between two programs written in C/C++ as a means to ensuring the correctness of the description provided to the HLS toolchain.
ACM TRETS, Vol. 18, No 1, Article 5 · paper
We design a spatial FPGA accelerator for LLM inference that assigns each operator its own hardware block and connects them with on-chip dataflow to cut memory traffic and latency.
IEEE Computer Architecture Letters · paper
We implement a virtual vector instruction set on a commercial Compute-in-SRAM device, and perform detailed instruction microbenchmarking to identify performance benefits and overheads.
IEEE Transactions on Computers · paper
Featured Paper in the May 2023 Issue
This paper proposes a Design Space Exploration framework to jointly optimize heterogeneous multi-core architecture, layer scheduling, and compiler mapping for serving DNN workloads on cloud FPGAs.
Invited Paper, DAC 2022 · paper
We show the advantages of the decoupled programming model and further discuss some of our recent efforts to enable a robust and viable verification solution in the future.
CVPR 2022 · paper · website · slides · poster · video
We propose CodedVTR, a flexible 3D Transformer on sparse voxels that decomposes attention space into linear combinations of learnable prototypes to regularize attention learning, with geometry-aware self-attention to guide training.
We propose an FPGA accelerator programming model that decouples the algorithm specification from optimizations related to orchestrating the placement of data across a customized memory hierarchy.
Invited Paper, ACM TRETS, Vol. 15, Issue 4, Article 38 · paper
Best Paper Award
We extend the previous work on RapidLayout with cross-SLR routing, placement transfer learning, and placement bootstrapping from a much smaller device to improve runtime and design quality.
Michal Servit Best Paper Award Nominee
We build a fast and high-performance evolutionary placer for FPGA-optimized hard block designs that targets high clock frequency such as 650+MHz.
arXiv 2025 · paper
We introduce Dato, a Python-based programming framework for dataflow accelerators that treats data communication as a first-class language feature. On AMD Ryzen AI, Dato achieves up to 84% hardware utilization for GEMM and a 2.81x speedup on attention kernels compared to state-of-the-art commercial frameworks.
We build an open-source Python framework implementing various NAS algorithms in a modularized and extensible manner.
MLIR Open Design Meeting (08/11/2022) · video · slides · website
CRISP Liaison Meeting (09/28/2022) · news · slides · website
We decouple hardware customizations from the algorithm specifications at the IR level to: (1) provide a general platform for high-level DSLs, (2) boost performance and productivity, and (3) make customization verification scalable.
MICRO 2021 ASCMD Workshop · paper · video
We propose a multi-node and multi-core accelerator architecture and a decoupled compiler for cloud-backed INFerence-as-a-Service (INFaaS).
Student Volunteer: FCCM'22
Reviewer: ICCAD 2022, 2023, TRETS, TCAS II
[ECE 2300] Digital Logic and Computer Organization
Head TA, Spring 2024
[ECE 5775] High-Level Digital Design Automation
Part-time TA, Fall 2022
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